1. Technical Field
The present invention relates generally to semiconductor memory devices and, in particular, to a semiconductor memory device and a repair method that employ programmable self-contained repairable cells to repair defect cells of a semiconductor memory device in a package state.
2. Background Description
In a semiconductor memory device such as a dynamic random access memory (DRAM) device, a memory cell plays an important role. Therefore, when a single cell in a group of cells has a defect, which-results in a malfunction of the-entire group of cells, the corresponding memory device is considered to be xe2x80x9ccondemned goodsxe2x80x9d. The greater the degree of integration of a DRAM, the greater the probability that some of the cells contained therein will have defects. However, the disposal of such devices as defective goods is an inefficient way to reduce mass product yields.
Accordingly, pre-constructing redundancy cells in DRAMs is a common way to obtain an acceptable device when that device is defective. In such a case, defect cells are replaced with redundancy cells when the defect cells are detected.
Redundancy cell repair technology fabricates sufficient fuses in a semiconductor memory device, and replaces any defect column lines and row lines with spare lines by applying a laser beam method. However, the laser beam method is mainly employed in a wafer state that precedes the packaging of a semiconductor device. Therefore, the repair process cannot be performed when defect cells are found after the device has been packaged. U.S. Pat. Nos. 6,011,734 and 5,764,577 disclose repair technology that is implemented in the packaging step of a semiconductor device.
U.S. Pat. Nos. 6,011,734 and 5,764,577 disclose repair methods that pre-construct spare cells in a DRAM device, store a defect cell address to a latch, inactivate a corresponding defect cell by comparing the latched address with the address accessed from the outside, and then activate redundancy circuits.
However, the above-mentioned U.S. Patents disclose redundancy cells established in the same physical structures as those of a memory cell array, and developed by the same processes as those of the memory cell array. Therefore, redundancy memory cells exhibit a high probability of having the same defect cells as those of memory cells. As a result, the repair processes for such devices are difficult in the case that defect redundancy cells are found.
The problems stated above, as well, as other related problems of the prior art, are solved by the present invention, a semiconductor memory device and a repair method that employ programmable self-contained repairable cells to repair defect cells of a semiconductor memory device in a package state. The semiconductor memory device and the repair method of the invention pre-construct redundancy logic cells in the peripheries of a memory cell array to replace defect cells of the memory cell array with the redundancy logic cells.
According to an aspect of the present invention, there is provided a semiconductor memory device. The device includes an address buffer for receiving an external address. A row decoder decodes a row address provided by the address buffer, and generates a word line selecting signal. A column decoder decodes a column address provided by the address buffer, and generates a bit line selecting signal. A memory cell array has a plurality of memory cells. Each of the plurality of memory cells is activated by a selection of a word line and a bit line by the word line selecting signal and the bit line selecting signal, respectively. A redundancy logic cell replaces defect cells in the memory cell array. A plurality of defect cell address latches store defect cell addresses corresponding to the defect cells in the memory cell array. The defect cells are detected in a memory test. A plurality of comparators output repair signals when an address stored in the plurality of defect cell address latches corresponds to the external address received by the address buffer. A redundancy controller generates a control signal to intercept the word line selecting signal and the bit line selecting signal corresponding to the defect cells in response to a repair signal outputted in a normal mode, and generates another control signal to enable a read/write operation of the redundancy logic cell in place of the defect cells.
According to another aspect of the present invention, there is provided a semiconductor memory device. The device includes a row address buffer for receiving an external row address signal. A column address buffer receives an external column address signal. A row decoder decodes a row address provided by the row address buffer, and generates a word line selecting signal. A column decoder decodes a column address provided by the column address buffer, and generates a bit line selecting signal. A memory cell array has a plurality of memory cells. Each of the plurality of memory cells is activated by a selection of a word line and a bit line by the word line selecting signal and the bit line selecting signal respectively. A redundancy logic cell replaces defect cells in the memory cell array. A plurality of defect cell row address latches store defect cell row addresses corresponding to the defect cells in the memory cell array. The defect cells are detected in a memory test. A plurality of defect cell column address latches store defect cell column addresses corresponding to the defect cells in the memory cell array. The defect cells are detected in the memory test. A plurality of first comparators output row repair signals when a defect cell row address stored in one of the plurality of defect cell row address latches corresponds to the row address provided by the row address buffer in a normal mode. A plurality of second comparators output column repair signals when a defect cell column address stored in one of the plurality of defect cell column address latches corresponds to the column address provided by the column address buffer in the normal mode. A redundancy controller generates a control signal to intercept the word line selecting signal and the bit line selecting signal corresponding to the defect cells in response to a row and a column repair signal, and generates another control signal to enable a read/write operation of the redundancy logic cell in place of the defect cells.
According to yet another aspect of the present invention, there is provided a semiconductor memory device. The device includes an address buffer for receiving an external address. A row decoder decodes a row address provided by the address buffer, and generates a word line selecting signal. A column decoder decodes a column address provided. by the address buffer, and generates a bit line selecting signal. A memory cell array has a plurality of memory cells. Each of the plurality of memory cells is activated by a selection of a word line and a bit line by the word line selecting signal and the bit line selecting signal respectively. A redundancy logic cell replaces defect cells in the memory cell array. A plurality of defect cell address storage devices store defect cell addresses corresponding to the defect cells in the memory cell array. The defect cells are detected in a test mode. A plurality of comparison devices output repair signals when an address stored in the plurality of defect cell address storage devices corresponds to the external address received by the address buffer. A plurality of redundancy control devices generate a control signal to intercept the word line selecting signal and the bit line selecting signal corresponding to the defect cells in response to the repair signals, and generate another control signal to enable a read/write operation of the redundancy logic cell, in a normal mode, in place of the defect cells.
According to still yet another aspect of the present invention, there is provided a semiconductor memory device. The device includes an address buffer for receiving an external address. A row decoder decodes a row address provided by the address buffer, and generates a word line selecting signal. A column decoder decodes a column address provided by the address buffer, and generates a bit line selecting signal. A memory cell array has a plurality of memory cells. Each of the plurality of memory cells is activated by a selection of a word line and a bit line by the word line selecting signal and the bit line selecting signal, respectively. First redundancy logic cells replace defect cells. Second redundancy logic cells replace the defect cells. A plurality of defect cell address latches store defect cell addresses corresponding to the defect cells. The defect cells are detected in a test mode. A plurality of comparators output repair signals when an address stored in the plurality of defect cell address latches corresponds to the external address received from the address buffer. A redundancy controller generates a control signal to intercept a pass of defect cell address signals of the row decoder and the column decoder in response to the repair signal, generates a first control signal to enable a read/write operation of the first redundancy logic cell when the memory cell array has the defect cells, and generates a second control signal to enable a read/write operation of the second redundancy logic cell when the first redundancy logic cell has the defect cells. The generating of the control signal, the first control signal, and the second control signal occurs in a normal mode.
These and other aspects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.